Part of the process in designing and developing an integrated circuit (“IC” or “chip”) is to verify the functionality of the chip prior to fabrication. It takes a significant amount of time for a design to be verified and finalized. Emulator circuit boards are used to model the design of the chip prior to actual fabrication. Such emulator circuit boards can use multi-pin devices, such as multiple field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like, to implement and simulate the gate logic of the chip design.
To verify a particular chip design, it is often mapped over to emulator boards. These boards traditionally provide for one or more multi-pin devices like FPGAs or CPLDs. One of these multi-pin devices may not be large enough on its own to model the entire chip design. Therefore, the high-level chip design may be partitioned into many smaller modules that are mapped into multiple multi-pin devices. The design complexity of the chip and the large number of pins on the multi-pin devices pose a challenge in designing the emulator boards. Test engineers not only account for the translation of the single chip design to one or more multi-pin devices, they also account for all of the interconnections between each of the pins of the group of multi-pin devices and other devices/connectors on the emulator boards by defining the input/output (I/O) configuration for each device and defining how each device connects to the rest of the system. Because the operation of these emulator boards depends on the accuracy of the design translation onto the boards, the mapping process is extremely important, challenging, and time consuming.
These interconnections are defined and modeled manually. The design engineers define the various interconnections in a spreadsheet, which is then used by a post processing tool in the course of designing the emulator boards. This design and mapping process is difficult and time consuming.